The effort to keep up with CMOS scaling, which relates to reducing the size of transistors in pursuit of Moore's Law, has led semiconductor industry in search for new transistor designs and use of alternative materials. In terms of design improvement, multi gate field effect transistors (MUGFET), such as FinFETs and Tri-gate FETs, are one of the strategies implemented. A MUGFET is a term used to describe a metal oxide semiconductor field effect transistor (MOSFET) incorporating more than one gate into a single device. A FinFET refers to a device in which the conducting channel is formed by a thin fin, which forms the body of the device. In terms of materials there is a great deal of interest in the use of germanium (Ge) as the channel material, instead of the state of the art silicon, due to its high bulk electron and hole mobility to boost up the transistor performance.
It is well known that reducing transistor sizes requires a minimization of series resistance towards the channel of the transistor to achieve high performance. This series resistance is composed of overlap resistance, extension resistance and contact resistance. In this respect, reducing contact resistance is one of the key parameters that will lead to reduction in series resistance thus achieving high performance.
One of the ways to reduce contact resistance is to convert the Ge present in the source and drain regions to low resistive nickel-germanide films by a well-known salmanide (self-aligned germanide) process (U.S. Pat. No. 7,517,765 B2). Salmanide process involves reacting thin films of deposited Ni with the underlying Ge substrate in a two-step rapid thermal (RTP) process. The first RTP step is usually done in the temperature range of 240° C. to 270° C., while the second RTP step is done in the temperature range of 300° C. to 400° C. In between the two RTP processes, unreacted or excess Ni is removed selectively by wet etch using acid mixtures as known to person skilled in the art. Salmanide process is a solid-solid reaction between deposited Ni and Ge and as such it involves consumption of Ge during the process of formation of nickel-germanide films as a result of rapid thermal process.
This approach faces several challenges as CMOS scaling continues. Firstly, the consumption of Ge during the germanidation reaction jeopardizes the geometry of the source and/or drain regions thus degrading the junction performances due to the dopants being pushed down to the Ge layers. Furthermore, the Ge material consumption results in formed germanide extending deeper into the Ge than the junction thereby forming short-circuit to underlying substrate. In order to overcome this challenge a layer of Ti is deposited in between two layers of co-sputtered Ni and Ge and a single RTP is done (U.S. Pat. No. 8,580,686 B1). However, such efforts have been silent concerning the challenge of reducing contact resistance.
Secondly, the applied etch chemistries, often, attack the formed metal germanide or Ge layers during the unreacted metal removal process step. Applying a single RTP process, in order to eliminate the use of selective etching process, at higher temperatures (≧300° C.) is a solution to overcome this challenge as known to persons skilled in the art. However, it results in large scale voiding due to enhanced Ge diffusion (Brunco et. al., Electrochemical and Solid State Letters, 11(2) (2008)). This can lead to higher leakage current and thereby degrading device performance, which is undesirable.
Hence, there exists a need in the art for a method to enable formation of NiGe contacts with reduced or no Ge consumption, while offering reduced contact resistance in the absence of degradation of device performance.